name: "4x4 Matrix Multiplier"
category: "DSP & Numerical Algorithms"
complexity: "Medium"
description: >
  Design a hardware accelerator for a 4x4 matrix multiplication (C = A x B).
  Input matrices consist of 16-bit signed integers. The module should take
  two 4x4 matrices as input and provide the resulting 4x4 matrix. Use valid /
  ready handshake signals for flow control.

sources:
  - "https://www.seas.ucla.edu/~baek/FPGA.pdf"
  - "https://github.com/fbv81bp/Matrix_multiplier"
  - "https://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/f2020/bjd86_lgp36/bjd86_lgp36/index.html"

interface:
  module_name: "matrix_mult_4x4"
  clocked: true
  ports:
    - name: "clk"
      type: "input"
      width: "1"
    - name: "rst"
      type: "input"
      width: "1"
    - name: "a_in"
      type: "input"
      width: "[255:0]"
    - name: "b_in"
      type: "input"
      width: "[255:0]"
    - name: "c_out"
      type: "output"
      width: "[511:0]"
    - name: "in_valid"
      type: "input"
      width: "1"
    - name: "in_ready"
      type: "output"
      width: "1"
    - name: "out_valid"
      type: "output"
      width: "1"
    - name: "out_ready"
      type: "input"
      width: "1"

target_platform:
  device_family: "AMD Xilinx Zynq-7000"

tasks:
  - name: "Minimum Resource Usage"
    constraints:
      max_lut: 259
      max_registers: 205
      max_bram: 2
      min_frequency: 100
    objective:
      goal: "minimise"
      target: "LUT"

  - name: "Maximise Performance"
    constraints:
      max_lut: 1000
      max_dsp: 16
      max_power: 1.5
    objective:
      goal: "maximise"
      target: "Fmax"
