name: "16-Tap Symmetric FIR Filter"
category: "DSP & Numerical Algorithms"
complexity: "Medium"
description: >
  Implement a 16th-order (17-tap) symmetric low-pass FIR filter.
  Input: 16-bit signed. Output: 32-bit signed.
  Symmetric coefficients (H[k] = H[16-k]): H0=65, H1=184, H2=419, H3=839, H4=1366, H5=1888, H6=2276, H7=2432, H8=2488.
  
  When in_valid is asserted, process the input sample. Assert out_valid for exactly one cycle when each output is ready. Pipeline depth is unrestricted. Output samples must appear in the same order as inputs. out_valid must be asserted in the exact same clock cycle as the valid sample_out data (not delayed).


sources:
  - "Nagaratnam et al. (2022) - Low-Power FIR Filter using Coefficient Reuse"
  - "Mittal et al. (2023) - 16th-order FIR for EEG Processing"

interface:
  module_name: "fir_16tap"
  clocked: true
  ports:
    - name: "clk"
      type: "input"
      width: "1"
    - name: "rst"
      type: "input"
      width: "1"
    - name: "sample_in"
      type: "input"
      width: "16"
    - name: "in_valid"
      type: "input"
      width: "1"
    - name: "sample_out"
      type: "output"
      width: "32"
    - name: "out_valid"
      type: "output"
      width: "1"

target_platform:
  device_family: "AMD Xilinx Spartan-7"

tasks:
  - name: "Power-Optimized FIR Filter"
    constraints:
      max_dsp: 0
      max_lut: 3000
      min_frequency: 100
      max_power: 0.93
    objective:
      goal: "minimise"
      target: "Power"
