name: "Pipelined 8-Tap FIR Filter"
category: "DSP & Numerical Algorithms"
complexity: "Medium"
description: >
  Implement an 8-tap symmetric low-pass FIR filter.
  Input: 8-bit signed. Output: 16-bit signed.
  Symmetric coefficients (H[k] = H[7-k]): H0=8, H1=21, H2=45, H3=54.
  Design must achieve single-cycle throughput (Initiation Interval = 1).

sources:
  - "Kartheek et al. (2020) - High-Speed FIR using APC-OMS"
  - "Mazuela et al. (2019) - Pipelined Systolic FIR"

interface:
  module_name: "fir_8tap"
  clocked: true
  ports:
    - name: "clk"
      type: "input"
      width: "1"
    - name: "rst"
      type: "input"
      width: "1"
    - name: "sample_in"
      type: "input"
      width: "8"
    - name: "in_valid"
      type: "input"
      width: "1"
    - name: "sample_out"
      type: "output"
      width: "16"
    - name: "out_valid"
      type: "output"
      width: "1"

  implementation_details:
    description: "When in_valid is asserted, process the input sample. Assert out_valid for exactly one cycle when each output is ready. Pipeline depth is unrestricted but should support single-cycle throughput. Output samples must appear in the same order as inputs. out_valid must be asserted in the exact same clock cycle as the valid sample_out data (not delayed)."

target_platform:
  device_family: "AMD Xilinx Zynq-7000"

tasks:
  - name: "High-Performance FIR Filter"
    constraints:
      min_frequency: 300
    objective:
      goal: "maximise"
      target: "Fmax"
