name: "Sobel Edge Detection Accelerator"
category: "AI/ML Accelerators"
complexity: "Hard"
description: >
  Implement a Sobel edge detection accelerator for FPGA.
  Input: 64x64 grayscale image (1 channel, 8-bit unsigned pixels, row-major streaming).
  Apply standard 3x3 Sobel kernels to compute horizontal (Gx) and vertical (Gy) gradients.
  Gx kernel: [[-1,0,1], [-2,0,2], [-1,0,1]].
  Gy kernel: [[-1,-2,-1], [0,0,0], [1,2,1]].
  Compute gradient magnitude using |Gx| + |Gy| approximation (saturate to 0-255).
  Use stride 1 and zero-padding 1 to produce 64x64 output feature map.
  Output: 8-bit unsigned gradient magnitude per pixel, row-major streaming.
  Module asserts 'done' for one cycle when complete.

sources:
  - "Joy et al. (2025) - High-Speed Hardware Edge Detection on FPGA (1905 LUTs, 253 FFs)"
  - "Mehra and Verma (2012) - Area Efficient FPGA Sobel Implementation (353 LUTs)"
  - "Chaple and Daruwala (2014) - Design of Sobel Operator on FPGA"

interface:
  module_name: "sobel_edge"
  clocked: true
  ports:
    - name: "clk"
      type: "input"
      width: "1"
    - name: "rst"
      type: "input"
      width: "1"
    - name: "start"
      type: "input"
      width: "1"
    - name: "pixel_in"
      type: "input"
      width: "8"
    - name: "pixel_valid"
      type: "input"
      width: "1"
    - name: "pixel_ready"
      type: "output"
      width: "1"
    - name: "pixel_out"
      type: "output"
      width: "8"
    - name: "out_valid"
      type: "output"
      width: "1"
    - name: "out_ready"
      type: "input"
      width: "1"
    - name: "done"
      type: "output"
      width: "1"

target_platform:
  device_family: "AMD Xilinx Spartan-7"

tasks:
  - name: "Resource-Efficient Sobel Edge Detector"
    constraints:
      max_lut: 500
      max_registers: 350
      min_frequency: 100
    objective:
      goal: "maximise"
      target: "Fmax"
