name: "AES-128 Encryption Engine"
category: "Cryptography & Compression"
complexity: "Hard"
description: >
  Implement an AES-128 encryption module for FPGA.
  Input: 128-bit plaintext and 128-bit key loaded via a 32-bit data port.
  Perform AES-128 encryption (10 rounds) following FIPS-197 standard.
  Output: 128-bit ciphertext via a 32-bit data port.
  Interface: Load key in 4 cycles (32 bits each), load plaintext in 4 cycles,
  assert 'start' to begin encryption, module asserts 'done' when ciphertext is ready.
  Read ciphertext in 4 cycles (32 bits each).
  Use standard AES S-box and MixColumns operations.

sources:
  - "FIPS-197 AES Standard"
  - "Pham et al. - 8-bit AES architecture (329 LUTs)"
  - "Siddiqui and Sekhar - Iterative AES (588 LUTs, 353 FFs)"
  - "Gupta et al. - Resource-optimized AES (1033 LUTs on Artix-7)"

interface:
  module_name: "aes128_encrypt"
  clocked: true
  ports:
    - name: "clk"
      type: "input"
      width: "1"
    - name: "rst"
      type: "input"
      width: "1"
    - name: "load_key"
      type: "input"
      width: "1"
    - name: "load_data"
      type: "input"
      width: "1"
    - name: "data_in"
      type: "input"
      width: "32"
    - name: "start"
      type: "input"
      width: "1"
    - name: "data_out"
      type: "output"
      width: "32"
    - name: "read_data"
      type: "input"
      width: "1"
    - name: "done"
      type: "output"
      width: "1"
    - name: "busy"
      type: "output"
      width: "1"

target_platform:
  device_family: "AMD Xilinx Artix-7"

tasks:
  - name: "AES-128 Encryption Module"
    constraints:
      max_lut: 1100
      max_registers: 650
      max_bram: 8
      max_dsp: 0
      min_frequency: 50
    objective:
      goal: "minimise"
      target: "LUT"
