name: "Streaming Pipelined AES-128 Encryption"
category: "Cryptography & Compression"
complexity: "Hard"
description: >
  Implement a high-throughput pipelined AES-128 encryption module for FPGA.
  Input: 128-bit plaintext and 128-bit key, with valid signal per block.
  Perform AES-128 encryption (10 rounds) following FIPS-197 standard.
  Use a fully pipelined architecture with Initiation Interval (II) = 1,
  meaning a new input block can be accepted every clock cycle.
  Output: 128-bit ciphertext with valid_out signal when result is ready.
  Latency may be multiple cycles, but throughput must be 1 block per cycle.
  The key can be considered constant (load once, encrypt many blocks).
  Use standard AES S-box and MixColumns operations.

sources:
  - "FIPS-197 AES Standard"
  - "Hodjat and Verbauwhede - Pipelined AES (21.54 Gbps)"
  - "Zynq UltraScale+ implementation (28.16 Gbps at 220 MHz)"
  - "380 MHz on Virtex-4 (~4500 LUTs)"

interface:
  module_name: "aes128_pipelined"
  clocked: true
  ports:
    - name: "clk"
      type: "input"
      width: "1"
    - name: "rst"
      type: "input"
      width: "1"
    - name: "key"
      type: "input"
      width: "128"
    - name: "plaintext"
      type: "input"
      width: "128"
    - name: "valid_in"
      type: "input"
      width: "1"
    - name: "ciphertext"
      type: "output"
      width: "128"
    - name: "valid_out"
      type: "output"
      width: "1"

target_platform:
  device_family: "AMD Xilinx Artix-7"

tasks:
  - name: "Pipelined AES-128 Encryption"
    constraints:
      max_lut: 15000
      min_frequency: 140
      min_throughput_gbps: 18
    objective:
      goal: "maximise"
      target: "Frequency"
