name: "Dual-Port Register File"
category: "Soft Processors & Memory"
complexity: "Easy"
description: >
  Design a dual-port register file for a small soft processor. The register file
  contains 32 registers, each 32 bits wide. It provides two independent read ports
  and one write port. Reads are combinational, and writes are synchronous on the
  rising edge of the clock when write enable is asserted. If a read address matches
  the write address in the same cycle, the read must return the write data (write
  has priority).

  Register 0 is a hardwired zero register. Reads from address 0 must always return
  32'b0, and writes to address 0 must be ignored.

  RESET: Synchronous active-high reset. When rst=1, all registers are cleared to 0
  on the next rising edge.

interface:
  module_name: "register_file_2r1w"
  clocked: true
  ports:
    - name: "clk"
      type: "input"
      width: "1"
      description: "Clock"
    - name: "rst"
      type: "input"
      width: "1"
      description: "Synchronous active-high reset"
    - name: "raddr1"
      type: "input"
      width: "5"
      description: "Read address for port 1"
    - name: "raddr2"
      type: "input"
      width: "5"
      description: "Read address for port 2"
    - name: "rdata1"
      type: "output"
      width: "32"
      description: "Read data for port 1"
    - name: "rdata2"
      type: "output"
      width: "32"
      description: "Read data for port 2"
    - name: "we"
      type: "input"
      width: "1"
      description: "Write enable"
    - name: "waddr"
      type: "input"
      width: "5"
      description: "Write address"
    - name: "wdata"
      type: "input"
      width: "32"
      description: "Write data"

target_platform:
  device_family: "AMD Xilinx Zynq-7000"

tasks:
  - name: "Compact Soft-CPU Register File"
    constraints:
      max_lut: 300
      max_registers: 1200
      max_bram: 0
      max_dsp: 0
      min_frequency: 100
    objective:
      goal: "minimise"
      target: "LUT"
