name: "8-Bit Single-Cycle ALU with Flags"
category: "Soft Processors & Memory"
complexity: "Medium"
description: >
  Design a single-cycle 8-bit ALU for a small soft processor. The ALU performs
  arithmetic and logical operations on two 8-bit operands (A and B) based on
  a 4-bit opcode. The result is 8 bits wide with additional flag outputs.
  
  OPCODE ENCODING:
    0000 (ADD):  Result = A + B
    0001 (SUB):  Result = A - B
    0010 (AND):  Result = A & B
    0011 (OR):   Result = A | B
    0100 (XOR):  Result = A ^ B
    0101 (NOT):  Result = ~A (B is ignored)
    0110 (SHL):  Result = A << 1 (logical left shift, LSB = 0)
    0111 (SHR):  Result = A >> 1 (logical right shift, MSB = 0)
    1000 (INC):  Result = A + 1 (B is ignored)
    1001 (DEC):  Result = A - 1 (B is ignored)
    1010 (CMP):  Result = 8'b0 if A == B, else 8'hFF (comparison)
    1011 (PASS): Result = A (pass-through, B is ignored)
    1100-1111:   Reserved (Result = 8'b0)
  
  FLAGS (active high, updated combinationally based on the result):
    zero:     Set if Result == 8'b0
    negative: Set if Result[7] == 1 (MSB indicates negative in signed representation)
    carry:    Set if ADD, SUB, INC, or DEC produces a carry/borrow out of bit 7.
              For SHL, carry is the MSB (bit 7) before shift.
              For SHR, carry is the LSB (bit 0) before shift.
    overflow: Set if ADD or SUB causes signed overflow (operand signs match but
              result sign differs). For other operations, overflow = 0.
  
  All outputs are purely combinational. There is no clock or reset.

interface:
  module_name: "alu_8bit"
  clocked: false
  ports:
    - name: "a"
      type: "input"
      width: "8"
      description: "First operand"
    - name: "b"
      type: "input"
      width: "8"
      description: "Second operand"
    - name: "opcode"
      type: "input"
      width: "4"
      description: "Operation selection (see opcode encoding)"
    - name: "result"
      type: "output"
      width: "8"
      description: "Operation result"
    - name: "zero"
      type: "output"
      width: "1"
      description: "Zero flag: set when result is zero"
    - name: "negative"
      type: "output"
      width: "1"
      description: "Negative flag: set when result MSB is 1"
    - name: "carry"
      type: "output"
      width: "1"
      description: "Carry flag: set on carry/borrow for arithmetic ops"
    - name: "overflow"
      type: "output"
      width: "1"
      description: "Overflow flag: set on signed overflow for ADD/SUB"

target_platform:
  device_family: "AMD Xilinx Spartan-7"

tasks:
  - name: "High-Frequency Soft-CPU ALU"
    constraints:
      max_lut: 80
      max_ff: 0
      max_bram: 0
      max_dsp: 0
      min_frequency: 100
    objective:
      goal: "maximise"
      target: "Fmax"
