name: "CRC-32 Generator"
category: "Cryptography & Compression"
complexity: "Medium"
description: >
  Implement a CRC-32 generator module with single-cycle throughput.
  The module continuously updates the CRC-32 value based on valid data bytes.
  
  CRC Configuration (Standard Ethernet/ZIP):
  - Polynomial: 0x04C11DB7
  - Initial Value: 0xFFFFFFFF
  - Input: Reflected (LSB first)
  - Output: Reflected
  - XOR Out: 0xFFFFFFFF
  
  Interface:
  - Resets to Initial Value.
  - Process `data_in` when `data_valid` is high. Hold value otherwise.
  - `crc_out` provides the current CRC value with 1-cycle latency.
  - `crc_valid` asserts whenever `crc_out` corresponds to valid data (1-cycle latency).
  
  Example:
  ASCII "123456789" -> 0xCBF43926

interface:
  module_name: "crc32_generator"
  clocked: true
  ports:
    - name: "clk"
      type: "input"
      width: "1"
      description: "Clock signal"
    - name: "rst"
      type: "input"
      width: "1"
      description: "Synchronous reset, active high"
    - name: "data_in"
      type: "input"
      width: "8"
      description: "Input data byte"
    - name: "data_valid"
      type: "input"
      width: "1"
      description: "High when data_in contains valid data to process"
    - name: "crc_out"
      type: "output"
      width: "32"
      description: "Current CRC-32 value (with final XOR applied)"
    - name: "crc_valid"
      type: "output"
      width: "1"
      description: "High when crc_out contains a valid CRC (after processing at least one byte)"

target_platform:
  device_family: "AMD Xilinx Zynq-7000"

tasks:
  - name: "Area-Efficient CRC-32 Generator"
    constraints:
      max_lut: 200
      max_ff: 50
      max_bram: 0
      max_dsp: 0
      min_frequency: 100
    objective:
      goal: "minimise"
      target: "LUT"
