name: "Iterative CORDIC Sin/Cos"
category: "DSP & Numerical Algorithms"
complexity: "Medium"
description: |
  Implement a clocked hardware module that computes sine and cosine for one input angle.

  Goal:
  - Compute sin(angle_in) and cos(angle_in) using fixed-point arithmetic.
  - This variation is area-oriented (not throughput-optimized).

  Fixed-point formats:
  - Input `angle_in`: signed 16-bit Q2.14, radians.
    Valid benchmark range: [-pi/2, +pi/2] (about [-1.57, +1.57]).
    Behavior outside this range is undefined.
  - Outputs `sin_out` and `cos_out`: signed 16-bit Q1.15.

  Interface protocol (simplified for v1):
  - `start` is a 1-cycle pulse with a valid `angle_in`.
  - Module processes the request and raises `done` for 1 cycle when output is ready.
  - `sin_out` and `cos_out` must be valid when `done` is high and remain stable
    until the next `start`.

  Accuracy target:
  - Compare against ideal mathematical sin/cos at the quantized input angle.
  - Required error per output: <= +/-0.00075 (about +/-24 LSB in Q1.15).

  Tiny implementation hint:
  - A typical area-efficient iterative CORDIC that meets this target uses about
    14-16 iterations with at least ~18-bit internal x/y/z precision.

interface:
  module_name: "cordic_sincos"
  clocked: true
  ports:
    - name: "clk"
      type: "input"
      width: "1"
      description: "Clock signal"
    - name: "rst"
      type: "input"
      width: "1"
      description: "Synchronous reset, active high"
    - name: "start"
      type: "input"
      width: "1"
      description: "Start computation (pulse high for one cycle)"
    - name: "angle_in"
      type: "input"
      width: "16"
      description: "Input angle, signed Q2.14 fixed-point (radians)"
    - name: "sin_out"
      type: "output"
      width: "16"
      description: "Sine result, signed Q1.15 fixed-point"
    - name: "cos_out"
      type: "output"
      width: "16"
      description: "Cosine result, signed Q1.15 fixed-point"
    - name: "done"
      type: "output"
      width: "1"
      description: "Pulses high for one cycle when result is ready"

target_platform:
  device_family: "AMD Xilinx Zynq-7000"

tasks:
  - name: "Area-Efficient Sine/Cosine Calculator"
    constraints:
      max_lut: 250
      max_ff: 150
      max_bram: 0
      max_dsp: 0
      min_frequency: 50
    objective:
      goal: "minimise"
      target: "LUT"
