name: "Pipelined CORDIC Sin/Cos"
category: "DSP & Numerical Algorithms"
complexity: "Medium"
description: >
  Implement a high-throughput sine and cosine calculator with single-cycle throughput.
  
  The module computes sin(angle) and cos(angle) for streaming input data.
  It must accept a new input sample every clock cycle (Initiation Interval = 1).
  
  FIXED-POINT FORMAT:
  - Input `angle_in`: 16-bit signed, Q2.14 format (radians).
    Valid range: [-pi/2, +pi/2] (approx. [-1.57, +1.57]).
  - Output `sin_out` / `cos_out`: 16-bit signed, Q1.15 format.
    Range: [-1.0, +1.0).
  
  INTERFACE PROTOCOL:
  - Streaming interface with valid signals.
  - When `in_valid` is high, `angle_in` contains valid data to process.
  - After a fixed latency (implementation-defined), results appear on
    `sin_out` and `cos_out` with `out_valid` high.
  - The module must sustain single-cycle throughput: a new input can be
    accepted every clock cycle regardless of latency.
  - `rst` clears any in-flight computations; outputs become invalid.
  
  ACCURACY:
  - Output values must be within ±0.001 (~32 LSBs in Q1.15) of ideal values.

interface:
  module_name: "cordic_sincos_perf"
  clocked: true
  ports:
    - name: "clk"
      type: "input"
      width: "1"
      description: "Clock signal"
    - name: "rst"
      type: "input"
      width: "1"
      description: "Synchronous reset, active high"
    - name: "angle_in"
      type: "input"
      width: "16"
      description: "Input angle, signed Q2.14 fixed-point (radians)"
    - name: "in_valid"
      type: "input"
      width: "1"
      description: "High when angle_in contains valid data"
    - name: "sin_out"
      type: "output"
      width: "16"
      description: "Sine result, signed Q1.15 fixed-point"
    - name: "cos_out"
      type: "output"
      width: "16"
      description: "Cosine result, signed Q1.15 fixed-point"
    - name: "out_valid"
      type: "output"
      width: "1"
      description: "High when sin_out and cos_out contain valid results"

target_platform:
  device_family: "AMD Xilinx Zynq-7000"

tasks:
  - name: "High-Throughput Pipelined Sine/Cosine"
    constraints:
      max_lut: 1000
      max_ff: 1000
      max_bram: 0
      max_dsp: 0
      min_frequency: 200
    objective:
      goal: "maximise"
      target: "Fmax"
