name: "7-Sample Median Denoising Filter"
category: "DSP & Numerical Algorithms"
complexity: "Medium"
description: |
  Implement a synchronous 1D median filter for denoising a stream of
  vibration-sensor samples that may contain short impulsive spikes.

  Each rising edge of `clk` captures one signed 12-bit two's-complement
  sample on `sample_in`. The filter operates on the 7 most recent captured
  samples.

  FILTER RULE:
  - Let x[n] be the sample captured on cycle n after reset is deasserted.
  - For every n >= 6, define W[n] = {x[n-6], x[n-5], ..., x[n]}.
  - Sort the seven values of W[n] in nondecreasing signed order.
  - The filtered result y[n] is the 4th value in that sorted list, i.e. the
    median of the 7-sample window.
  - Comparisons must use signed two's-complement ordering.
  - Equal values remain separate samples when selecting the median. Do not
    discard duplicates.
  - `sample_out` must be exactly one of the seven captured samples in W[n];
    do not average, saturate, or otherwise transform the selected value.

  OUTPUT TIMING:
  - The output for W[n] must appear one clock cycle later.
  - If y[n] is the median for samples captured through cycle n, then on
    cycle n+1 `out_valid` must be high and `sample_out` must equal y[n].
  - The first valid output therefore occurs one cycle after the 7th sample
    after reset deassertion is captured.
  - Example: if the 7th post-reset sample is captured on cycle T, then
    `out_valid` must still be low on cycle T. The first cycle on which that
    window's median may appear is cycle T+1.
  - After a full 7-sample history exists, `out_valid` must remain high on
    every cycle until reset is asserted, because each new input sample
    creates a new 7-sample window.

  RESET:
  - `rst` is synchronous and active-high.
  - While `rst` is high, clear all stored samples and drive `out_valid` low
    and `sample_out` to 0.
  - After reset is deasserted, the next captured sample becomes the first
    sample of a new stream. No pre-reset samples may contribute to any
    post-reset output.

interface:
  module_name: "median7_denoiser"
  clocked: true
  ports:
    - name: "clk"
      type: "input"
      width: "1"
      description: "System clock; one sensor sample is captured per cycle"
    - name: "rst"
      type: "input"
      width: "1"
      description: "Synchronous active-high reset"
    - name: "sample_in"
      type: "input"
      width: "12"
      description: "Signed two's-complement input sample from the noisy 1D sensor stream"
    - name: "out_valid"
      type: "output"
      width: "1"
      description: "High when `sample_out` contains the median of the most recent 7-sample window from the previous cycle"
    - name: "sample_out"
      type: "output"
      width: "12"
      description: "Signed two's-complement filtered output sample"

target_platform:
  device_family: "AMD Xilinx Zynq-7000"

tasks:
  - name: "Area-Efficient 7-Sample Median Denoiser"
    constraints:
      max_lut: 260
      max_ff: 128
      max_bram: 0
      max_dsp: 0
      min_frequency: 180
    objective:
      goal: "minimise"
      target: "LUT"
